A 0.06 mm2, 0.9 pJ/bit, 25 Gb/s Optical Receiver Front-End Module in 65 nm CMOS

This paper presents the measurement results of a 0.9 pJ/bit, 25-Gb/s optical receiver front-end based on the active-voltage current-feedback (AVCF) transimpedance amplifier (TIA). The proposed TIA core circuit has the stable operation and the increased gain compared with the conventional TIAs. The occupied chip area with I/O and DC pads is 660 μm x 580 μm (= 0.38 mm
²
) and the proposed analog front-end TIA occupies only 360 μm x 160 μm (≈ 0.06 mm
²
). The proposed module operates at 25-Gb/s with a supply voltage of 1.0 V and consumes only 22.6 mW.