Optimized Timing Aware ATPG for At-Speed Test of Cell Internal Faults

Achieving high structural defect coverage is extremely critical to achieve low defective parts per million (DPPM) and to eliminate the need for additional system level tests. New defect oriented test methods such as cell-aware tests (CAT) have been introduced to improve test quality on advanced technology nodes. In general, addition of new fault models bring in challenges with regard to test cost impact and execution turn-around for large design scales and complexities. In this paper, we specifically focus on the issue of pattern count and runtime issues introduced by the need for timing aware automatic test pattern generation (ATPG) for testing cell-internal small-delay defects. We present novel strategies and CAT test generation methodologies to shrink the size of the fault list for timing aware ATPG (TA-ATPG) to target only the critical and relevant cell-internal small-delay faults. The experimental results by using the proposed methods on a large-scale design are shared to highlight the efficacy of the proposed solution in terms of runtime reduction and test efficiency improvement.