Simulation of Trap-Induced Noise Characteristics in 3-nm Complementary FET

This study investigates trap-induced noise characteristics in a 3-nm node complementary FET transistor (CFET) through TCAD simulations and theoretical calculations. A noise power spectral density (PSD) model tailored for the 3D gate-all-around structure is developed. Through theoretical calculations, the dependence of noise PSD on trap profiles and bias conditions is investigated.