Impact of Time Delay Schemes on Reliability Degradation during Program/Erase Cycling in HZO-based FeFETs

The commercialization of HZO-based FeFETs is hindered by issues such as MW degradation and poor endurance. In this study, we systematically investigate degradation suppression using time delay schemes. Our findings reveal that symmetric time delay during cycling fails to effectively mitigate MW and SS degradation. Interestingly, we observe that the optimization of MW or SS can be achieved through asymmetric delay (i.e., time delay only after program or erase). It’s found that delay after programming (P-delay) effectively suppresses MW degradation, while delay after erasure (E-delay) proves effective in mitigating SS degradation. This study offers valuable insights into the reliability optimization of HZO-based FeFETs.