Design and Analysis of CMOS based VCO with Common Source Topology

This paper reports a single-ended VCO based on a common source configuration-based delay stage. CMOS 180nm technology has been used to design the proposed circuit. The stacking technique has been applied to VCO to reduce the power consumption. Common source configuration-based VCO design provides a higher frequency from 3.556 GHz to 9.997 GHz by varied bias voltage of load from 0V to -0.2V. Maximum power consumed with 1.8V is 2.1 mW at 9.997 GHz. Further, output frequency varies from 2.649 GHz to 7.161GHz with varied bias voltage from 0.1V to 0.3V. Maximum power consumption at 7.161GHz is 1.382 mW with 1.8V supply voltage. With the use of the stacking technique, a significant reduction in power consumption has been achieved, and maximum power is reduced to 0.612 mW at 1.8V with a frequency of 3.941 GHz. The proposed VCO design provides a good frequency tuning range while consuming less power.