LP 8T SRAM: Design of New Technique SRAM With Reduced Power Consumption

In the landscape of VLSI design, where memory hierarchy plays a pivotal role, two pressing challenges take center stage: power dissipation and propagation delay. The primary goal of the research is to craft a low-power SRAM tailored for the demands of 16nm technology. Leveraging the 16nm PTM model for PMOS and NMOS components, the approach aims to usher in an era of efficient semiconductor design. The SRAM design achieves a remarkable reduction in power consumption without compromising on acceptable propagation delay and maintaining a compact physical footprint. Recognizing the vital role SRAM plays in the intricate memory hierarchy, the approach diligently tailors the method to ensure that power gating becomes an integral component in the conventional SRAM design, leading to substantial enhancements in power efficiency and signal delay. A comprehensive series of simulations and analyses, conducted with the aid of LTspice, serves to validate the effectiveness of the innovative approach, promising a brighter future for electronic devices. As a significant contribution to the evolution of these devices, the work stands as a valuable milestone in the quest for efficiency and excellence in the world of VLSI design.