Back-side Design Methodology for Power Delivery Network and Clock Routing

This paper presents a backside (BS) design methodology for optimizing both power delivery network (PDN) and clock routing in 3nm. A unit converter (UC) has been integrated on the backside with BS-PDN to minimize IR-drop. Additionally, our backside buffer cell with backside contact enables backside clock routing. Experimental results show that BS-PDN mitigates 57.7% IR-drop compared to FS-PDN, and UC integration further reduces IR-drop by 10.3% and package IR-drop by 83.91 %. Furthermore, backside clock routing improves clock power by 32% and full-chip power-delay product by 16%.