Memory Access Acceleration Through Architecture Design for Edge SoCs

The design of the SoC architecture plays a pivotal role in defining the computational power and performance of Artificial Intelligence of Things (AIoT) products. The CPU serves as the core controller of the SoC, thereby forming the fundamental aspect of its architectural design. This paper presents an SoC architecture featuring a CPU passthrough strategy, which significantly diminishes CPU memory access latency by up to 71% and boosts CPU performance by a minimum of 8% at specific frequencies.