LLM Based End-to-end Branch Predictor Optimization Generator

The branch predictor is one of the crucial components influencing the performance of modern processors. This study aims to explore the optimization space for configurable parameters within the branch predictor and, based on the parameter results, generate RTL code end-to-end through a large language model, thereby enhancing the efficiency of processor microarchitecture design. In the research process, we take the TAGE branch predictor as an example, explore it towards the real-time control domain function library, and construct a DSP processor branch predictor for an eight-stage pipelined dual-issue architecture based on LLM.