Energy-Efficient Adiabatic MTJ/CMOS-Based CLB for Non-Volatile FPGA

High flexibility, infinite reconfigurability, and fast design-to-market of FPGAs make them a promising platform for modern applications, such as IoT, medical, and automotive applications. Energy and area limitations are challenging in these applications since many of these applications have limited power and hardware resources. Accordingly, the energy- and area-efficient design of FPGAs is of great importance. In this paper, an adiabatic non-volatile hybrid CMOS/MT J logic-in-memory-based configurable logic block (CLB) has been proposed and compared to its state-of-the-art counterparts. The simulation results show that the proposed design has 98%, 98%, 97%, 97%, 96%, and 92 % lower energy consumption compared to CMOS counterparts for frequencies of 1, 2.5, 5,10,20, and 40 MHz. Also, compared to its adiabatic counterparts, the proposed design has at least 74%, 70%, 69%, 69%, and 46% lower energy consumption for frequencies of 1, 2.5, 5, 10, and 20 MHz, respectively. Also, the proposed design has at least 74
^%
fewer transistors compared to its counterparts. Furthermore, the energy saving of the proposed design for different tunnel magnetoresistance (TMR) is almost consistent. In addition, the proposed design keeps its superiority in energy saving over its counterparts for different power supply voltages.