I. Introduction
A resistive random-access memory made up memory cell comprising of two metals and insulator as metal-insulator-metal (MIM) structure. An external voltage source across the ReRAM cell triggers a change in resistance from a high resistance state (HRS), (OFF state) also mentioned as logic with value ‘0’ to a low resistance state (LRS), (ON state) mentioned as logic with value’ 1‘. The reverse of above-mentioned resistive change from low to high completes one full cycle. The resistive switching (RS) or resistive change mechanism is reflected as the underline cause behind the change in resistive state of the single ReRAM cell.