Understanding and Mitigating Hardware Interference Channels on Heterogeneous Multicore

Contention for shared microarchitectural resources is a significant challenge for using modern heterogeneous multicore processors in safety-critical real-time applications. In this talk, I will first discuss major microarchitectural interference channels in modern multicore architecture. I will describe why microarchitectural designs aiming to achieve high memory-level parallelism (MLP), such as non-blocking cache and banked cache/DRAM organizations, could also become problematic interference channels from a real-time perspective. To illustrate their potential dangers, I will explain several effective “attack” strategies that have been shown to cause massive cross-core interference in real multicore platforms. Next, I will focus on the industrial challenge put forth by ARM in 2022, which is based on an augmented reality head-up display case-study from the automotive domain. I will discuss the impact of “aggressor” workloads on the performance of the case study's real-time applications on a real heterogeneous multicore platform (Jetson Nano). I will then present our software-based solution to achieve desired real-time performance without resorting to over-provisioning. Lastly, I will discuss the limitations of our approach and the need for better hardware support.