FPGA Implementation of AES Algorithm for CAN FD

In this paper, we present an AES encryption module to solve the problem of plain text transmission during CAN FD communication, which is easy to be stolen. After software synthesis and implementation, the module occupies only 1379 LUTs and 399 Slices, and can meet the timing convergence requirements at $\mathbf{2 6 0 M H z}$. The throughput rate reaches 3.328 Gbps. The AES encryption module achieves high speed and high efficiency data encryption under the condition of low area occupation. It is suitable to be integrated into CAN FD controllers and other communication modules with strict area requirements.