Design of a 12-bit 30MS/s Pipeline ADC for Image Sensors

In this paper, a 12-bit 30MS/s pipeline ADC for CMOS image sensors is designed based on smic 0.11um process. This design adopts a SHA+2.5bit × 5+2bit flash structure. The main circuits include sample-and-hold circuit and dynamic comparators, operational transconductance amplifiers, multiplying digital to analog converter(MDAC). The main OTA adopts a gain-boost structure in order to meet the large gain and bandwidth requirements, and uses an innovative common-mode feedback to reduce power consumption, at the same time, the capacitance reduction technique is used to reduce the power consumption of the rear stage OTA. Simulation results show an SFDR of 79.6dB and an ENOB of 11.54bit at a sampling clock frequency of 30 MHz and an input frequency of 10 MHz. Power consumption is 44 mW at a supply of 3.3 V.