A 5.8GHz Band LNA in TSMC 0.18μm CMOS Technology

This article discusses a noise reduction method for a 5.8GHz Low Noise Amplifier (LNA) circuit designed for CMOS technology, specifically TSMC. The LNA employs a parallel cascode structure, where the circuit’s gain can be adjusted continuously by manipulating capacitance and inductance. Implemented using 180 nm CMOS technology, the analog gain achieves 15.1 dB, with noise measured at 1.77 dB at the center frequency. Input and output matching are both below -10 dB, ensuring stability of the circuit.