Design of FIR Filter Using a Novel Approach with High-Speed Multiplier

Systems for digital signal processing and communication require finite impulse response filters that offers linear phase response and stability. The proposed multiplier, implemented using Xilinx Vivado, targets the reduction of high delay and power consumption associated with existing designs. The development of the bit pair recoding algorithm is a key contribution, enhancing the efficiency of filter design for VLSI applications. The project aims to improve the speed and effectiveness of VLSI systems by employing efficient multipliers and FIR filters. Filter architectures can vary based on area, power consumption, and time delay, making optimization crucial. The outcome of the paper includes a detailed analysis comparing the new multiplier with existing designs to demonstrate its superior performance in terms of speed, power efficiency, and overall effectiveness in FIR filter applications.