Impact of Device Parametrics on a 10nm Gate Length SOI n-FinFET

This research paper presents a comprehensive analysis of the behaviour of a Tri-gate Silicon-On-Insulator (SOI) n-FinFET with a gate length of 10nm. Innovative gate stacking featuring SiO
2
, HfO
2
oxide layer, and a ferroelectric film along with a TiO
2
spacer are two features of the device that improve performance in low-power applications. Utilizing TCAD models, the research delves into crucial subthreshold variables, including threshold voltage and subthreshold swing and other output parameters like the drain induced barrier lowering (DIBL) which are analysed using Silvaco simulations. Systematic investigation of the effects of the incorporating TiO
2
spacer and gate stacking found the subthreshold swing value of the optimised FinFET design to be 136 mV/dec and the DIBL value for the optimised design is found to be 63.10 mV/V. Changes in the I-on and I-off values for the optimised design are also observed. The effects of the variation of the gate metal work function
$(\Phi_{\mathrm{m}})$
are also studied. Our research helps to better comprehend unique design configurations for sub-10nm FinFETs, to continue advancing semiconductor technology and create more effective integrated circuits.