Low clock power standard cell flip-flop topologies

In this paper, we present the design and evaluation of several low power flip flop topologies to address the problem of large clock energy consumption for low data activity factor applications. We present a comparative analysis of clock energy, total energy, timing and the tradeoffs involved. A few promising topologies which can be used in place of conventional flops for lowering the clock energy without compromising too much on the delay and reliability are further investigated for low voltage robustness. Delay scaling with lower voltages is also examined. We show that low power flops can reduce clock energy between 20-40% at low data activity factors at an area overhead of 10-15%. Our paper also presents a complete framework to compare these flops. Standard cell versions of the flops were designed, laid out and compared post layout to obtain these results