Contents I. Introduction
In Very-Large-Scale-Integrated (VLSI) circuit design, Static Timing Analysis (STA) is the major Sign-Off checks for timing viewpoint due to advantages of (1) the simplicity to make constraints for Setup/Hold timing, (2) scalability to more and more integrated design as well as (3) the good correlation to SPICE simulation. After all Front-End (logical) and Back-End (physical) implementations, Timing Closure is the final step to achieve all timing criteria to bring the design to fabrication. This phase includes repetitive iterations of STA checks, commands making for Engineering Change Order (ECO), ECO Automatic Place and Route (P&R or APR) runs and Parasitic Extractions, which would consume much computing resource and designers’ efforts. Designers have the trade-off of accepting features or performance drops from commencing target to keep the delivery time. As the continuous evolution of Technology, there are more and more challenges to have the success for Timing Closure and for Chip Tape-Out. Tweaker has proven the strength of an effective tool for ECO making, which results in higher timing quality, less hardware/designer cost and speed up the delivery time.
