Compressor based Approximate Multipliers for Neural Network Accelerators

As several image and video processing applications gain popularity, the approximate computing has gained importance to effectively utilize the available channel bandwidth. As multipliers are the computationally intensive components of neural networks, the aim of this paper remains to approximate it and reduce the number of components utilized for its implementation. This paper proposes six approximate multipliers based on approximation of 4 to 2 compressors for Neural Networks. The design 1 utilizes exact 8x8 multiplier with 2, 3 and 4-input AND, XOR and OR gates for approximate compressor with 6.25% error, The design 2 utilizes only 2-input XOR, AND and OR gates for approximate compressor with 37.5% error. The designs 3 to 6 are the combinations of multiplexer based approximations carried out with an error of `5.8% to 20%. The designs are developed in Verilog HDL and implemented for 28nm high-K CMOS technology based Zynq FPGA (XC7Z100-2FFG1156) in Xilinx Vivado Tool. The proposed design 5 proves to be reliable along with the less total path delay of at least by 2.47% to 7.81% and the power dissipation being minimum by at least 5.6% to 14.02%. How ever design 5 trades off area by 2.98% to 6.94%, where design 6 proves to be a good choice. From results, the proposed designs 5 and 6 to be good choice for approximate multipliers.