Aging -aware Path Timing Prediction via Graph Representation Learning

In advanced CMOS technology, aging degradation dominated by Negative Bias Temperature Instability (NBTI) has emerged as a significant challenge for the timing closure of circuits. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. Traditional aging-aware timing analysis flows find it difficult to achieve a tradeoff between computational overhead and accuracy. In this paper, we propose an aging-aware path timing prediction framework via graph representation learning. We customize a graph transformer network (GTN) to generate efficient path graph representation with global attention mechanism. Exper-imental results demonstrate that our proposed framework can obtain accurate timing path prediction with MAPE score of 3.75 %, and can achieve acceleration of over 7000 times compared to SPICE simulation with acceptable accuracy loss.