RLCkt II: Deep Reinforcement Learning via Attention-Aware Sampling for Analog Integrated Circuit Transistor Sizing Automation

The sizing of circuit transistors that meet design specifications in analog integrated circuit (IC) traditionally relies on the intuition and experience of human experts, posing challenges that are labor-intensive and time-consuming, particularly as circuit complexity increases. Compared to mainstream optimization algorithms that exhibit slow optimization speeds and unstable solutions when dealing with large-scale analog IC, this study introduces RLCktII, a breakthrough improvement built upon the advanced RLCkt. For the first time, it incorporates an attention mechanism combined with deep reinforcement learning into the domain of automated analog integrated circuit transistor sizing. Through the attention mechanism, it dynamically discerns the most distinctive input data, enhancing the deep reinforcement learning model's capability to handle complex tasks. RLCkt II was evaluated on two industrial-scale analog integrated circuits: LDO and R2R. After one and a half days of training, our RLCkt II agent achieved an average improvement of 28.71 % and 7.94% in convergence accuracy over the state-of-the-art RLCkt. In the same design tasks, RLCkt II demonstrated a speed advantage nearly a hundred times faster than the Genetic Algorithm (GA) while also ensuring greater design precision.