Automatic Multi-Parameter Tuning for Logic Synthesis with Reinforcement Learning

Logic synthesis serves as the intermediate stage between abstract logic and physical implementation. It involves various logic optimization and technology mapping algorithms, which are iteratively applied to the circuit. The multi-parameter tuning for logic synthesis is the process of generating a sequence of logic optimization and technology mapping operators with multiple parameters. The Quality-of-Result (QoR) is significantly impacted by different recursive arrangements of optimization commands and parameter selections of technology mapping operators. Nowadays, the order of calling algorithms is usually determined by heuristics. The heuristic becomes unacceptable if based on a large exploration space and test design. To address this issue, we utilize reinforcement learning (RL) with the proximal policy optimization (PPO) algorithm to train an agent to effectively generate the optimization and mapping sequence. To acquire adequate features to aid decision-making, we utilize the Graph Isomorphic Network (GIN) with edge feature aggregation capability to learn circuit representations and use circuit scalars as state representations for the reinforcement learning agent. To allow the agent to learn from historical operations, we utilize the Long Short-Term Memory (LSTM) to uncover the relationships between different operators within a single sequence. Additionally, we address the issue of selecting the parameter for the technology mapping operator by framing it as a multi-class classification problem and training a classifier to identify the optimal parameter. We evaluated the effectiveness of our model using the EPFL arithmetic benchmark. The result shows that our model achieved an average improvement of 9.93% in area and 13.62 % in depth on each test design over the greedy algorithm. Furthermore, we achieve a significant improvement of 65.79 % in area and 37.79 % in delay on the biggest test design. These findings highlight the potential of our approach to enhance logic synthesis and technology mapping for large circuits.