GraphRTL: An Agile Design Framework of RTL Code from Data Flow Graphs

As the increasing demand for large and complex signal processing requirements, the efficient and fast design of signal processing circuits becomes an important issues. Agile design offers a new approach for rapid hardware design cycles. While this approach is a standard for software design, how to adapt it to hardware design properly remains an open question. In our work, we propose a framework for agile software and hardware co-design named GraphRTL. The tool addresses the challenge of designing hardware for Digital Signal Processing (DSP). Instead of direct coding and debugging iteration, we employ data flow graphs (DFG) and control flow graphs (CFG) to automatically generate RTL code. The input to GraphRTL is the flow graph of the designed circuit. Subsequently, the tool checks the graphs, reconstructs it, and then translates it into a configuration file for the compiler. Finally, the compiler autonomously generates the corresponding software to hardware code and RTL code. Compared to the traditional design route, GraphRTL enhances design efficiency and broadens the design space. In our experiments, we achieved up to an 70% reduction in design time while maintaining a 5 to 10% reduction in hardware overhead for the designed circuits.