A Variation-Aware CMOS Platform for Multi-Level Memristor Characterisation

Memristors could be potentially used in both multi-bit data storage and analogue computation, thanks to their programmable resistance. However, there are three common practical challenges to programme memristors to multiple resistive levels. First, the programmed resistance is unstable due to the device's intrinsic randomness and relaxation. Second, the memristor's transient resistive response to external stimuli is stochastic. Third, programming is unachievable if the target level is beyond the memristor's operational region. To overcome these challenges, this work proposes a novel characterisation methodology, which could implement multi-level memristor programming by experimentally identifying the memristor's multi-level capability and then determining the corresponding resistance ranges to accommodate its non-idealities. To automate the proposed methodology, a mixed-signal CMOS system is proposed. It mitigates device variations by providing flexibility for reconfiguring pulsing schemes. Furthermore, it provides up to 4.9V voltage pulses and enhanced reading accuracy for a wide-range resistive load (2kΩ to 5MΩ).