Low-Power Ternary Multiplication Using Approximate Computing

This study is being conducted with the intention of presenting a novel approximate computation technique that is capable of performing ternary multiplication while consuming a minimal amount of electricity. The low-power design methodology that utilizes carbon nanotube field-effect transistors (FETs) is utilized in order to propose a carry-truncated ternary multiplier, error compensation circuits, and 2 ×2 ternary multipliers with varying degrees of precision. This methodology is employed for the goal of suggesting a carry-truncated ternary multiplier. A approach that allows for the customization of the precision of the design is recommended for the design of energy-efficient 6 ×6 approximation ternary multipliers. This advice is offered in the context of the design process. Through the usage of HSPICE simulation, it has been verified that the energy benefits of the suggested 6 × 6 approximation ternary multipliers have been proven within the realm of energy benefits. When compared to the previous approximate multiplier-based design, the proposed approximate design demonstrates an improvement of 41.8% in mean absolute percentage error and 82.8% in power-delay product. Both of these improvements are significant. Both of these improvements are significant. In order to verify that the user’s need for the accuracy of ternary multiplication is met, image processing applications are carried out with the help of the provided approximation designs.