Modeling of Content addressable memory using 2D Reconfigurable Transistors

Content-addressable memory (CAM) compares input search data with stored data, returning the address upon a match. CAMs offer high-speed parallel search, making them ideal for associative memory applications. CAMs are categorized into binary (BCAMs) and ternary CAMs (TCAMs). BCAMs store two states and require an exact match for a successful search, while TCAMs can store a third state, “don’t care” or “X”, always resulting in a match. Traditionally, CAMs are implemented using CMOS static random-access memory (SRAM). However, SRAM-based CAMs use ≥ 9 transistors, increasing the area and power dissipation. Recently, 2D reconfigurable transistors (RFETs) have emerged as a promising technology for TCAMs. 2D-RFET TCAMs offer high on/off ratio, low power consumption, non-volatile data storage, and low area requirement, using only 1T for realizing a CAM [1] .