Small Signal Analysis of Nanosheet Transistor for sub-THz Frequency Considering Intersheet Capacitances and Modified Admittance Parameters

Maintaining iso-(I
ON
/C
gg
) is the prime objective of demonstrating emerging devices for DC/RF applications. This paper proposes a small-signal Nanosheet FET (NSFET) analysis, considering intersheet capacitances and width optimization with a modified admittance parameter approach. Using well-calibrated TCAD models, we analyzed different width-optimized configurations of NSFET, i.e., (D1) NSFET with multiple vertical sheets of width (W
Sh
) 25 nm (Fig. 2a); (D2) two-stack of vertical sheets with W
Sh
=25nm (Fig. 2b); (D3) single sheet NSFET with W
Sh
of 55nm (Fig. 2c). The proposed configurations have the same effective width (W
eff
). The performance metrics, such as ON current (I
ON
), gate capacitances (C
gg
), cut-off frequency (f
T
), transconductance (g
m
), etc., are optimized for all three configurations, and thus, the peak of f
max
~322 GHz is obtained for the optimized D2 configuration. Therefore, design guidelines are worth exploring for NSFET operating in sub-THz range with optimized number (#) of stacks & # sheets.