A Model for Generating Wafer Defect Maps

In response to the scarcity of available high-quality wafer defect maps, this paper proposes a method for generating wafer defect maps based on deep convolutional generative adversarial network (DCGAN) and variational autoencoder (VAE) models. To ensure a high degree of similarity between generated data and real data, this study uses the WM-811K dataset as a foundation. Firstly, a subset of real wafer defect maps with obvious features and clear defect patterns is extracted from this dataset. Subsequently, the extracted data is subjected to denoising, size normalization, and morphological augmentation to obtain the training dataset. During model training, different generative models are trained based on the characteristics of different types of defects. For instance, for wafer defect maps with high spatial symmetry such as edge-ring and donut shapes, DCGAN models are trained to generate such defect maps. Conversely, for wafer defect maps with poor symmetry and pattern consistency, such as scratches, VAE networks yield better generative results.