Modelling, Data Mapping, and Evaluation of Analog Multiply-And-Accumulate Components in Quantized CNNs

Hardware-acceleration of convolutional neural networks (CNNs) with analog integrated circuits has garnered significant interest from both industry and research. Advancements in neural network software architectures and algorithms however remain out-of-step with circuit-level design innovations in building power- and area- efficient analog hardware for the matrix multiply-accumulate (MAC) operations: The computing workhorse of modern CNNs. This article proposes a modelling framework for evaluating non-ideal analog MAC circuit components in quantization-aware training (QAT) CNNs. The CNN network parameters including image and kernel data are mapped to a physical crossbar array model of analog-in-memory computing (AIMC) or serialized MACs. Different mapping strategies such as weight stationary (WS), output stationary (OS) and partial-product quantization (PPQ) techniques are explored. The implications of using non-ideal AIMC components incorporating gain, nonlinearity, noise non-idealities, and mismatch variations are investigated. The hardware-aware modelling framework provides a valuable toolkit for analog designers to estimate the effects of block/circuit-level analog MAC design specifications on the overall system-level CNN network accuracy. Our hardware-aware CNN evaluations reveal simple CNNs can tolerate analog non-idealities to an extent, therefore guide analog designers on how best to optimize the analog MAC circuits in a power- and area-efficient manner to avoid hardware over-design.