A Novel Si/SiC Heterojunction Trench MOSFET with Electron Tunneling Enhanced and P+ Shielding Region for Improved On-State Resistance

A silicon (Si)/silicon carbide (SiC) heterojunction trench MOSFET with an electron tunneling enhanced (ETER) and P+ shielding region (P+SLD) (HJ-TMOS) is proposed to overcome the issue that the inversion channel mobility is poor in SiC. An improved channel mobility is obtained in the upper Si layer while the SiC drift layer is capable to provide high breakdown voltage simultaneously. The introduction of the ETER brings about a significantly decreased heterojunction barrier width, thus enhancing electron tunneling effect. Therefore, the heterojunction resistance (R
hj
) does not lead to a prominently degraded on-state resistance (R
on
). In addition, the gate oxide is well shielded by the P+SLD. As a result, not only the conduction characteristic, but also the blocking characteristic is significantly improved. Numerical analysis with Silvaco TCAD has been carried out and the results show that compared with the conventional trench MOSFET with a P+SLD under the gate trench (P-TMOS), the breakdown voltage (BV) and specific on- resistance (R
on,sp
) are improved from 1449V and 4.55mΩ•cm
²
for the P-TMOS to 1710V and 2.07mΩ•cm
²
for the HJ-TMOS, respectively. Meanwhile, the peak electric field in the gate oxide (E
ox,peak
) at V
DS
=1200V is relieved from 3.57MV/cm to 2.45MV/cm.