A Mixed-Precision DNN Compiler for Robotic Computing on FPGA

Adopting deep learning models in robotic systems such as simultaneous localization and mapping (SLAM) attracts great interests from the community. The deployment of deep learning models on resource-constrained robotic edge system poses significant challenges due to their limited computational resources. Network architecture search(NAS)-based quantization is proven to achieve a great balance between network performance and hardware efficiency, which typically results in a mixed-precision network. Many mixed-precision accelerators have been developed as well to support computing mixed-precision networks manually. A software-hardware interface is thereby needed to au-tomatically map mixed-precision networks onto mixed-precision accelerators. In this paper, we have developed a custom compiler framework for maximized speed-up through optimal mapping to the 2–8 bit acceleration, better scheduling on the core and minimum runtime overhead. Experiments show that, through our automated compilation approach, the mixed-precision models deployed on the ZCU102 FPGA achieves maximumthroughput (524 GOPs for VGG16, 423GOPs for UndeepVo, 705 GOPs OpenPose), meeting the real-time computing requirements for robotic DNNs.