A 37.2-fs, -254.6-dB FoM, 47.9-to-56.4 GHz PLL using Tightly Coupled Dual-core VCO with Implicit 4th Harmonic Extraction Technique

This paper presents a 47.9-to-56.4 GHz phase-locked loop (PLL) with 37.2-fs jitter and -254.6-dB FoM. The proposed PLL used a tightly-coupled VCO with the implicit 4
^th
harmonic extraction technique, enabling to output both the fundamental and the 4
^th
harmonic frequency simultaneously. The proposed tightly coupled VCO increases the Q factor and reduces the deterioration of capacitive mismatch on phase noise, resulting in improved overall jitter and figure of merit (FOM) of the PLL. The chip prototype is fabricated using a 65 nm CMOS process. The measured PN of the VCO at 10 MHz offset varies from -126.3 dBc/Hz to -129.5 dBc/Hz depending on output frequency. The measured jitter of the PLL using the proposed VCO is 37.2 fs.rms with the FOM of -254.6 dB. The power consumption of the PLL excluding buffers is 25 mW.