A K-Band CMOS Power Amplifier using an Analog Predistortion Linearizer with 22.1 dBm Psat and 0.9° AM-PM Distortion

This paper presents a K-band CMOS power amplifier (PA) using the 65-nm CMOS process. To improve linearity, an analog predistortion linearizer using a cold-FET and a variable inductor is proposed. Unlike conventional cold-FET linearizers, which face limitations in improving amplitude-to-phase (AM-PM) distortion at high output power, the proposed linearizer compensates both AM-PM distortion and amplitude-to-amplitude (AM-AM) distortion of the PA. Especially, the linearizer has a phase-lag characteristic at medium output power and phase-lead characteristic at high output power, which compensates for AM-PM distortion of the PA up to high output power. The implemented PA achieved a peak power-added efficiency (PAE) of 34.4%, saturation output power (P
sat
) of 22.1 dBm, and P
1dB
of 19.44 dBm at 27 GHz. Also, AM-PM distortion of only 0.9° was achieved through the proposed linearization technique. Linear output power satisfying error vector magnitudes (EVMs) of -25 dB and -30 dB were measured at 16.5 dBm and 14.9 dBm, respectively.