I. Introduction
Quantum computers hold the promise of tackling complex problems that are currently intractable. Solid-state quantum computers consist of arrays of qubits that are implemented using various solid-state technologies and operate at extremely low temperatures [1]. For higher scalability and to limit the number of interconnects to room temperature (RT), there have been proposals for fully integrated CMOS readout and BiCMOS architectures with on-chip clock generation [2]. To achieve a target qubit fidelity of 99.99%, it is necessary that the integrated phase noise (PN) of the VCO / PLL be less than 0.57 °[3], and low-noise amplifiers (LNA) with a Kelvin range of noise equivalent temperature (NET) [2]. Extensive research has been conducted on SiGe HBTs, and it has been observed that they exhibit lower levels of noise at RT compared to their CMOS counterparts. Furthermore, SiGe HBTs have a high transit frequency of 500 GHz and a high current gain β. These properties make HBTs the ideal choice for designing LNAs. On the other hand, low 1/f noise, reduced corner frequency, and high β of SiGe HBTs offer the possibility, along with effective design techniques, to develop VCOs with optimized phase noise and low power consumption. However, while there has been significant progress in modeling and characterization of low-frequency noise in CMOS down to 4K, advanced SiGe HBTs still lack proper modeling. This paper aims to address this gap by focusing on DC and RF characterization in the first part, which is crucial to extract small signal parameters such as base resistance (rb) and emitter resistance (re). The second part of the study delves into high-frequency noise ranging from 100 MHz to 12 GHz, highlighting the existence of an optimal bias region for low-noise and power optimization. Finally, a comparison study of low-frequency noise between 293 K and 4 K is presented, including corner frequency fc, flicker noise coefficient (KF), and Figure of Merit (FoM) fc/fT.