A 5G FR2 n260/n259 Phased-Array Transmitter Front-End IC in 28-nm CMOS FD-SOI with 3-Stack Power Amplifier Employing OPA-Based Bias Scheme and Cross-Tied Inductor Topology

This paper presents a 16-element 5G FR2 n260/n259 phased-array transmitter front-end integrated circuit implemented in a 28-nm CMOS fully depleted silicon on insulator device technology. A differential 3-stack configuration, an operational amplifier-based bias scheme, and a cross-tied inductor topology are employed in the power amplifier for high output power, stability, and reliability. The developed transmitter achieves out-put power of >14.2/9.4 dBm/element at an error-vector-magnitude of 5.6% (DFT-s OFDM 64QAM) with transmitter efficiency of >10/4.8%/element for n260/n259 bands.

I. Introduction

5G wireless technology plays a crucial role in meeting the ever-growing demand for high-data rate, low-latency, and increased connectivity [1]. Within the 5G frequency spectrum, FR2 extends into the mmWave band, which enables the potential for even higher communication speeds and capacities. This rapid trend has driven the field of solid-state circuits toward the development of numerous 5G FR2 transceivers (TRXs) [2]–[8]. The 1^st developed 39-GHz phased-array TRX is reported in [2], successful integrations of both phased-array TRX and intermediate-frequency integrated circuit (IFIC) are introduced in [3], [4], a frequency reconfigurable dual-band phased-array TRX is presented in [5], and phased-array TRXs employing Doherty power amplifiers (PAs) for high back-off efficiency are demonstrated in [6]–[8].