A 0.2-to-39.2GHz 66.2-fs Jitter and −71.3dBc Spur Sub-Sampling PLL Using DAC-Based Constant Control Voltage Compensator and Quad-Mode 2nd Harmonic Filtering Oscillator

In this paper, an ultra-wideband sub-sampling PLL with low jitter and spur is proposed. A digital-to-analog converter based constant control voltage compensator is introduced to achieve constant control voltage of oscillator in PLL. Here, the less control voltage variation leads to short charge/discharge time of charge pump, which obtains fast frequency hopping. To improve the in-band phase noise and spur performances, the constant control voltage is optimized in the linear range of oscillator and the current matching range of charge pump. Besides, the mm-wave quad-mode 2
^nd
harmonic filtering oscillator is integrated in the PLL to achieve the low out-of-band phase noise within a wide frequency range. The tail resonator is injected in four times of common-mode current, which enhances the 2
^nd
harmonic shaping. The proposed PLL is fabricated in a 40-nm CMOS technology. Measurements exhibit an output frequency range from 0.2 to 39.2GHz. The PLL achieves 66.2fs
rms
jitter and –71.3dBc reference spur. The typical power consumption is from 21.5 to 30.8mW. The PLL occupies a core area of 0.4mm
²
.