RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism

In recent years, the training of DNN has always occupied a large resource cost, especially when edge device are operating accordingly. This article introduces a RISC-V based Compression Processing Element (RCPE) based on 64-bit RISC-V, which insides RISC-V processor into DNN training processors to support more flexible and comprehensive training of artificial neural networks. It also has three technical improvements. Firstly, RCPE has a method of Flexibly Controlling the Reuse of Data(FCRD) through the RISC-V instruction. Secondly, RCPE has an instruction based Redundant Computation Skip Mechanism(RCSM) that predicts sparse and duplicate fields in advance. Thirdly, RCPE includes a scheme to Quickly Adjust the Calculation Format(QACF) based on the instruction stream, which converts the input into various variable precision forms. Through the evaluation of the 28nm CMOS process, the RCPE achieved well performance.