Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology

As Semiconductor technology advances, there is a growing demand for energy-efficient digital circuits in various applications, including portable devices and data centers. FinFET (Fin Field Effect Transistor) technology has emerged as a promising solution to meet these demands. FinFET technology, a leading innovation in the semiconductor industry, is known for its capability to deliver exceptional performance and energy efficiency. This paper provides an overview of the designing and simulation of counter using 10nm FinFET technology in LT -spice, a popular electronic circuit simulation tool. Conventional CMOS technology faces challenges related to short-channel effects as technology scales down, resulting in performance degradation. Power consumption and noise are reduced by 57.13%, 46.02% when counter are designed, implemented with FinFET based D-Flip Flop. Incontrast, FinFETs offer superior resistance to short-channel effects and have emerged as a promising solution for advancing technology scaling. Finally, the results obtained from the proposed Jhonson Counter, asynchronous counters using FINFET are better when compared to Static CMOS Logic.