Design and Analysis of Ternary 2-Trit Comparator Based on FinFET Models

The introduction of multivalue logics has been proven to be advantageous in the realm of digital system design, as it aids in diminishing circuit complexity and enhancing energy efficiency. Within the field of multivalue logic, ternary logic is generally considered an innovative approach. This article presents a comprehensive overview of the design of a ternary 2-trit comparator using 18nm FinFET technology, implemented via the use of the Virtuoso tool offered by Cadence. The evaluation of the comparator's performance is carried out by a comparison of the results obtained using SVT and HVT FinFET models. The obtained simulation results reveal power consumption values of 81.35 and
$\mathbf{111.8}\ \boldsymbol{\mu} \mathbf{W}$
, transient delay values of 49.57 and 29.46 ns, and power delay product values of 4032.51 and 3293.62
$(\mathbf{x}\ \mathbf{10}^{-\mathbf{15}}\ \mathbf{J})$
for the SVT and HVT FinFET models, respectively. The proposed design of a ternary 2-trit comparator can be used for data sorting, decision making applications.