A Generic UVM Verification Framework Based on Two-Stage Comparison for Protocol-Agnostic Data Streams in Digital Designs

Unlike data packets governed by specific protocols, the data stream of input and output ports in signal processing blocks within chips lacks flags such as start and end, hindering individual data packet comparison during verification. A protocol-agnostic data stream verification framework based on the universal verification methodology (UVM) is proposed. Two-stage comparison is employed to match the outputs of the reference model and the design under test (DUT), enabling real-time comparison of the protocol-agnostic data stream. The stimulus generator operates independently outside the UVM environment, delivering stimuli to the DUT through a generic data interface. Featuring high-level abstraction and easy scalability, this framework is suited for complex scenarios with multi-module cascading. Finally, it facilitates the construction of a digital down converter (DDC) verification platform, and running on an Intel Core i7-8086K processor with 6 cores, achieved comparison of all module data streams in just 9 seconds. Moreover, this platform has also been extended to other different digital designs, all completing verification at a rapid pace.