Enhancing Low-Power SRAM Performance with FinFET Integration: A 10T Model Analysis

This research paper presents a 10-transistor (10T) SRAM cell that was developed for low power consumption and optimized utilizing Fin Field-Effect Transistor (FinFET) technology. The cell was designed to be optimal for low power consumption. Moving away from the conventional Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) frameworks, the work makes use of HSPICE simulations in order to investigate the performance increases that can be achieved through the incorporation of FinFETs at the 16nm technological node. A number of key performance metrics, including Average Power Consumption, Power Dissipation, Power Delay Product (PDP), and Signal Delay, are analyzed in order to highlight the advantages of our FinFET-based SRAM cell in comparison to conventional designs, particularly with regard to energy economy and operational speed. The findings shed insight on the potential of FinFET technology to advance SRAM architecture, which holds the promise of making substantial contributions to the development of memory systems that are more efficient, faster, and reliable. The purpose of this study is to highlight the innovative nature of the 10T SRAM cell architecture, which is responsible for pushing the limits of low-power, high-performance memory technology.