A Hierarchical BRAM/URAM Buffer for SNN

Applications such facial recognition, social networking and automated translation are well-known by their exponential growth in size and level of complexity. Such applications are the real-world examples of machine learning which are computationally modeled using neural network. Executing such operations are bounded by the needed memory to store and transfer datasets into computational units. Access rate and storage capacity are related, in somehow, to the type of memory and its structure. In domain-specific architectures, on_chip memories are usually utilized as data memory because they allow wider busses and higher operation rate, however they are less dense that off_chip memories such as DRAMs. Examples of on_chip memories are Block RAM (BRAMs) and UltraRAMs (URAMs). While both memories are equivalent in latency and speed, URAM is considered denser because of its capability to cascade and create larger memory without reversely impacting the frequency. In this work, we propose a hierarchical hybrid input buffer to store weight and spikes of spiking neural network accelerator. The buffer is designed as a combination of BRAMs and URAMs where BRAMs represent the lower layer (closer to processing unit) while URAM are the upper layer. We tested our design on Xilinx Ultrascale Zynq 104 FPGA device and we found that our design can run on a higher frequency with less hardware resources and BRAM/URAM utilization comparing with the state-of-the-art.