High-Speed Operational Amplifier Based on a Modified “Folded” Cascode

A CBjT high-speed operational amplifier (op-amp) has been developed and studied, which differs from known in its modified input stage (IS), as well as the architecture of the intermediate “folded” cascode (FC). The proposed circuits IS and FC circuits solve the problem of increasing the maximum slew rate of the output voltage (SR) in large-signal mode by more than 10 times. In the LTspice environment, computer simulation of an op-amp on complementary bipolar transistors was performed, which shows that the use of the developed transient correction circuits makes it possible to increase SR from 103 V/μs to 1408 V/μs. The logarithmic amplitude-frequency characteristics of the op-amp under study are given for different options for its inclusion - with and without general negative feedback. The leading and trailing edges of the op-amp transient process were studied with an input rectangular pulse signal with an amplitude of 5V at different values of the capacitance of the additional correction capacitor $C_{\mathbf{k1}}$. The simulation results are presented in the form of a table that establishes the relationship between the numerical values of the maximum rate of rise of the output voltage of the op-amp and the capacitance $C_{\mathbf{k1}}$. The considered op-amp is recommended for use in various automation devices and communication systems, for example, discrete-analog filters on switched capacitors, high-speed ADC drivers, etc.