Comparative Evaluation of 10 kV SiC MOSFET Power Module Insulation Ability Through Chip Neighborhood Range Electric Field Modelling

Insulation failure is the primary problem of medium-voltage (MV) silicon carbide (SiC) MOSFET power modules restricting the advanced performances of SiC chips, which is induced by the electric field concentration caused by both the packaging and SiC chips. This paper establishes the insulation ability comparative evaluation of 10 kV SiC MOSFET power module through proposed chip neighborhood range (CNR) electric field model based on technology computer-aided designer (TCAD), where the model is defined and calibrated as prerequisite. The influence of chip and packaging structure variation on the electric field distortion on the insulation weak point at the interface between chip and encapsulation material as well as the insulation enhancement method are comparatively evaluated, demonstrating that bonding wires will significantly weaken the insulation ability regardless of protection. Three types of 10 kV half-bridge SiC power modules are fabricated and partial discharge test is carried out to effectively verify the evaluation results, showing that apparent charge of module with ten bonding wires of 20.7 pC is much larger than that with four bonding wires of only 1.2 pC.