Electric Field Optimization for Enhanced Insulation in 10kV SiC MOSFET Power Modules Based on Chipwall Integration

The insulation ability is crucial for the long-term operation of medium voltage power modules, and the concentration of internal electric fields at insulation weak points of medium voltage power modules will have a strong impact on them. This article investigates new electric field concentration points in medium voltage power modules, in addition to traditional three-phase points, and proposes an electric field optimization method for verification. Technology computer aided design (TCAD) simulation analysis of the insulation weak area under the high DC voltage stress shows that the maximum electric field strength at the interface between the packaging material and the chip terminal is higher than 18 kV Imm, which will lead to insulation degradation of the silicon gel. Therefore, the optimization design is proposed, and the method of reducing the internal electric field stress of silicon gel by pasting the chip insulation wall(Chipwall) on the chip surface is verified through simulation. Finally, two types of 10kV power modules with or without chip insulation walls were fabricated and subjected to partial discharge (PD) testing to verify the insulation improvement of the optimized design. Through optimization, under 8.5kV DC, the partial discharge pulse of the power module withchip wall structure was much lower than that of themodule without chip wall, proving the effectiveness of chip wall for insulation enhancement.