Design and Modeling of Quad Gate-Stacked Nano Sheets Finfet Device and Its Implementation in Digital Applications

In this paper, the nanosheet device has been designed at a 30 nm technology node using Tanner Computer Aided Design (TCAD) tool. The device has been calibrated with the reference model. Further modifications have been made to design a Quad Gate Stacked Nano-sheet FinFET device. The device has been compared with FinFET and Nano-sheet device existing in the literature. The analysis of the device simulation results reveals that the designed device has low leakage current and step sub-threshold slope, making it suitable for low-power applications. The leakage current is 9.85 × 10
⁻¹⁴
A, and the sub-threshold slope is 26.7 mV. Also, the potential and electric field in the region along the channel have been analyzed. The device modeling has been done for its implementation in circuit designing. Also, the inverter has been designed incorporating the designed devices’ model file.