Efficient Hardware Implementation of Hash Algorithm SHA-3 for IoT Information Security

SHA-3 is a typical third-generation secure hashing algorithm. In order to improve the performance of SHA-3 and better apply it in IoT devices, a new pipeline structure is designed using a two-stage unrolling structure, and different path cutting is carried out at each stage to shorten the critical path. As a result, the frequency and throughput have been improved. The 64-bit round constant involved in the calculation is simplified to 7 bits, which reduces the storage space required for the round constant. The data buffer is added between data padding and processing to reduce the padding module waiting period caused by the long processing period of the core processing module. The experimental results show that the SHA-3 core function has excellent performance with the maximum throughput of 20.78Gbps and 20.43Gbps on Xilinx's Virtex-6 and Virtex-5 field programmable gate array (FPGA), respectively.