The Role of the Gate Resistance and Device Variability on the Dynamic Performance of Parallel SiC Power MOSFETs

This paper presents an analysis of the fast switching transients with parallel SiC power MOSFETs. It is observed that two SiC power MOSFETs in parallel fail during the double-pulse-test measurements at turn-off events for high load currents. The failure originates from the internal oscillations caused by the circuit layout, package parasitics, and device variability. An advanced modeling procedure taking into account the de-vice process variations, the internal distributed gate resistance, and the broadband electromagnetic parasitic behavior of the switching circuit and package was used to analyze the internal oscillations, which could not be probed by any measurements. It is shown that the channel doping variation, causing threshold voltage
$V_{\text{th}}$
mismatch, can lead to a high gate stress during turn-off. An integrated lumped internal gate resistance
$R_{\text{g,int,L}}$
is demonstrated to be beneficial for the safe switching operation more than the intrinsic gate distributed resistance
$R_{\text{g,int,D}}$
.