Towards Vertical GaN-Power ICs: Co-integration of Lateral HEMTs and Vertical Power CAVETs

We report on the development of the co-integration of a common lateral HEMT (high-electron mobility transistor) technology with vertical GaN devices based on a CAVET (current aperture vertical electron transistor) design on the same chip/die. Process and device design parameters are discussed and optimized. Large-area vertical devices with drain-currents/breakdown-voltages of up to 20 A/250 V and lateral devices with breakdown voltages VDS > 30 V are demonstrated on the same die and subsequently diced and packaged. Finally, multi-pulse tests in a double pulse test setup (inductive load) are demonstrated with lateral HEMTs as a gate-driver stage and a vertical CAVET with maximum drain current >4 A at 250 kHz and VIN = 40 V on a total chip area of 3 mm
²
, This work demonstrates a technology platform for a direct integration of vertical GaN power devices with lateral functionality.